1. Field of the Invention
The present invention relates generally to an automatic synthesizing technology of logic circuits. More particularly, the invention relates to a logic circuit synthesizing method and a logic synthesizing system optimizing logic circuits for satisfying given constraint, such as area, delay and so forth. Further specifically, the invention relates a logic circuit synthesizing technology optimizing logic circuits for satisfying given constraint, such as area, delay and so forth under a premise of design modification.
2. Description of the Related Art
As the conventional automatic synthesizing technology of logic circuits, a technology disclosed in L. Stok et al., ASICs (BooleDozer: Logic Synthesis for ASICs), July, 1996, IBMJ. RES. Development, pp 407-430) and so forth, is made reference to, for example.
In this technology, in the optimization process of the circuit, management has been effect as to which part the circuit before optimization corresponds. Therefore, when modification of the circuit is effected, while rough identification of a partial circuit concerning which portion of the circuit has been modified, storing of the circuit before modification for the portion other than that modified associating with modification of the circuit, is not possible.
On the other hand, in Y. Watanabe et al., xe2x80x9cIncremental Synthesis for Engineering Changesxe2x80x9d Proceeding of IEEE International Conference on Computer Design, 1991, pp 40 to 43, there has been disclosed a method for maintaining a circuit after design modification modified only by modification of connection of wiring, substantially equivalent to the circuit before design modification. However, it cannot be guaranteed that any modifications are only modifications of connections of the wiring and a condition before design modification is maintained. Also, since the disclosed method performs calculation concerning addition of wiring using a logic information of the overall circuit, process is complicate and application for a large scale circuit is difficult.
As set forth above, the conventional automatic synthesizing technology of the logic circuits encounters the following problems.
A first problem is that when a part of the circuit is subject to design modification, storing of the circuit before modification for the portion other than that modified, associating with modification of the circuit, is not possible
The second problem is that it cannot be guaranteed that the condition before modification is stored, and since addition of wiring is performed on the basis of logic information of the overall circuit, process becomes complicate to cause difficulty in application for a large scale circuit.
A first object of the present invention is to provide a logic circuit synthesizing method and system which generates new circuit for peripheral portion of the circuit portion subjecting design modification and enables to maintain circuit condition before design modification in the case where a part of the circuit is subject to design modification.
A second object of the present invention is to provide a logic circuit synthesizing method and system which can output a result of synthesis satisfying constraint, such as area, delay and so forth as required for the circuit, comparable with result of synthesis in the logic circuit synthesizing method not premised to design modification, even when design modification is premised.
A third object of the present invention is to provide a logic circuit synthesizing method and system premised to design modification not depending upon circuit scale.
According to the first aspect of the invention, a logic circuit synthesizing method for optimizing a given logic circuit for satisfying a given area, delay and other constraints, comprising the steps of
dividing an inputted logic circuit into a plurality of partial circuits on the basis of a circuit information of the logic circuit,
outputting a resultant circuit by providing logic optimization per each partial circuit for satisfying constraint and synthesizing the partial circuits provided logic optimization,
upon design modification of the logic circuit, dividing the resultant circuit in the same manner of preceding time of division, and
outputting a resultant circuit by providing logic optimization only for the partial circuit, for which design modification is effected, re-using the former resultant circuit for the partial circuits other than that subject to design modification and synthesizing the modified partial circuit which is newly optimized and the re-used partial circuits.
In the preferred construction, in division of the logic circuit into the partial circuits,
circuit elements forming the logic circuit are classified into circuit elements having fan out greater than or equal to 2 and circuit elements having fan out 1,
with taking the circuit element having fan out greater than or equal to 2 as a unit of division, circuit elements having fan out 1 connected to input terminal of the circuit elements having fan out greater than or equal to 2 are aggregated for combination, and
on the basis of the classification result and the combination result, the logic circuit is divided into partial circuits.
In another preferred construction, in division of the logic circuit into the partial circuits,
circuit elements forming the logic circuit are classified into circuit elements having fan out greater than or equal to 2 and circuit elements having fan out 1,
with taking the circuit element having fan out greater than or equal to 2 as a unit of division, circuit elements having fan out 1 connected to input terminal of the circuit elements having fan out greater than or equal to 2 are aggregated for combination by sequentially tracing the circuit elements having fan out 1 up to reaching to the circuit element having fan out greater than or equal to 2, and
on the basis of the classification result and the combination result, the logic circuit is divided into partial circuits.
In another preferred construction, in logic optimization process of the partial circuit,
logic optimization is performed for all of combinations of adjacent divided partial circuits,
as a result of the logic optimization, selecting combination of partial circuits the closest to a constraint of the circuit input upon optimization, and
the combination of the partial circuits is taken as a new partial circuit.
According to the second aspect of the invention, a logic circuit synthesizing system for optimizing a given logic circuit for satisfying a given area, delay and other constraints, comprises
logic dividing means for dividing an inputted logic circuit into a plurality of partial circuits,
constraint input means for inputting area, delay or other constraint given for the partial circuits,
division optimizing means for executing logic optimization for each of the partial circuits of the logic circuit input for the first time and performing optimization in order to satisfy the constraint,
newly optimizing means for newly executing logic optimization only for the partial circuit, in which modification is caused, when modification of the circuit is effected,
re-using means for holding the results of logic optimization at the first time with respect to the partial circuits other than the partial circuit for which modification is effected,
combining means for combining the partial circuits held by the re-using means and the partial circuit newly performed logic optimization, and
synthesized result outputting means for outputting a synthesizing result by the division optimizing means or combination result by the combining means.
In the preferred construction, the logic circuit synthesizing system further comprises first time circuit input means for initially inputting the logic circuit for the logic circuit, for which design modification is expected, modified partial circuit inputting means for performing input of the partial circuit after design modification, and former time circuit input means for inputting the logic circuit as a result of synthesis for the former time.
In another preferred construction, the logic dividing means comprises circuit element classifying means for classifying circuit elements having fan out 1 and circuit elements having fan out greater than or equal to 2 concerning circuits elements forming the logic circuit, and cone generating means for performing division with taking the circuit element having fan out greater than or equal to 2 as a unit for division and aggregating circuit elements having fan out 1 connected to the input terminal of the circuit elements having fan out greater than or equal to 2.
In another preferred construction, the cone generating means performs division with taking the circuit element having fan out greater than or equal to 2 as a unit for division and aggregating circuit elements having fan out 1 connected to input terminal of the circuit elements having fan out greater than or equal to 2 are aggregated for combination by sequentially tracing the circuit elements having fan out 1 up to reaching to the circuit element having fan out greater than or equal to 2.
In another preferred construction, the divided logic optimizing means comprises logic optimizing means for combination for performing logic optimization for all of combinations of adjacent divided partial circuits, combination judging means for selecting a combination of the partial circuits closest to the constraint of the circuit input upon optimization as a result of the logic optimization, and cone merge means for taking the selected combination of the partial circuits as a new partial circuit.
In another preferred construction, the logic dividing means comprises circuit element classifying means for classifying circuit elements having fan out 1 and circuit elements having fan out greater than or equal to 2 concerning circuits elements forming the logic circuit, and cone generating means for performing division with taking the circuit element having fan out greater than or equal to 2 as a unit for division and aggregating circuit elements having fan out 1 connected to the input terminal of the circuit elements having fan out greater than or equal to 2, and
the divided logic optimizing means comprises logic optimizing means for combination for performing logic optimization for all of combinations of adjacent divided partial circuits, combination judging means for selecting a combination of the partial circuits closest to the constraint of the circuit input upon optimization as a result of the logic optimization, and cone merge means for taking the selected combination of the partial circuits as a new partial circuit.
According to another aspect of the invention, a storage medium storing a computer program performing logic circuit synthesis for optimizing a given logic circuit for satisfying a given area, delay and other constraints, comprising the steps of
dividing an inputted logic circuit into a plurality of partial circuits on the basis of a circuit information of the logic circuit,
outputting a resultant circuit by providing logic optimization per each partial circuit for satisfying constraint and synthesizing the partial circuits provided logic optimization,
upon design modification of the logic circuit, dividing the resultant circuit in the same manner of preceding time of division, and
outputting a resultant circuit by providing logic optimization only for the partial circuit, for which design modification is effected, re-using the former resultant circuit for the partial circuits other than that subject to design modification and synthesizing the modified partial circuit which is newly optimized and the re-used partial circuits.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.